Micron Technology Inc

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the 16,777,216-bit banks is organized as 2048 rows by 256 columns by 32 bits.

The M25PE16 is a 16Mb (2Mb x 8-bit) serial-paged Flash memory device accessed by a high-speed SPI-compatible bus. The memory can be written or programmed 1 to 256 bytes at a time using the PAGE WRITE or PAGE PROGRAM command. The PAGE WRITE command consists of an integrated PAGE ERASE cycle followed by a PAGE PROGRAM cycle.